The present invention relates to a semiconductor integrated circuit designing method, a semiconductor integrated circuit designing apparatus, and a recording medium storing semiconductor integrated circuit designing software and, more particularly, to a method, apparatus, and recording medium for verifying a lithography rule check (to be referred to as an LRC hereinafter) when correcting data during the formation of a mask for fabricating a semiconductor integrated circuit.
Semiconductor integrated circuits capable of containing a huge number of transistors by using the most advanced processes have various layout patterns in order to, e.g., implement functions and reduce chip areas.
To ensure a good yield of lithography in the scene of production, a lithography simulation that changes focusing, the exposure amount, and the like over broad ranges is used to check the possibilities of various layout patterns.
In the conventional MDP (Mask Data Processing)/OPC (Optical Proximity Correction), the implementation of a layout pattern formed by a designer is the final target, and addition, deletion, and the like of fine patterns are performed to approach the design value as close as possible.
In normal semiconductor design, a schematic corresponding to a rough wiring diagram is formed before the formation of a layout pattern, in order to optimize the electrical characteristics and timings.
In the conventional LRC verification, however, the LRC operation is started from a layout diagram formed after this schematic formation without using the information generated by the schematic formation. That is, the operation sequence is constructed and the setting conditions of each tool, error filters, and the like in the operation sequence are adjusted in order to implement the layout pattern formed by the designer.
This operation sequence has steps of outputting design data found to have no error on the basis of a design rule check (to be referred to as a DRC hereinafter), performing the MDP/OPC, performing the LRC, and checking an error.
This conventional sequence is constructed without taking the electrical characteristics into consideration. That is, the MDP/OPC is executed without using any information concerning the electrical characteristics, and the presence/absence of an error of a lithographed layout pattern is checked by the LRC, thereby increasing the verification load of error determination.
More specifically, if an error is detected in the conventional sequence, a lithography engineer alone cannot determine the contents of correction in many cases. As a consequence, the error information is fed back to a designer, the designer corrects the design, and the turn around time (to be referred to as the TAT hereinafter) increases. Alternatively, even when an error is found by the LRC, a portion requiring no layout pattern correction sometimes exists if the information concerning the electrical characteristics is taken into account. If a lithography engineer alone must correct this error, however, he or she corrects even a portion as described above, and the correction load increases.
A reference disclosing the conventional LRC verification technique is as follows.    Japanese Patent Laid-Open No. 2005-308944